Semiconductor memory

ABSTRACT

A dynamic RAM is arranged such that a common data line in each of the non-selected ones of the divided memory arrays is connected to a pair of common source lines of a sense amplifier corresponding to the memory array concerned, whereby the potential of the common data line is set at a medium level which is substantially equal to the potential of the data lines by utilizing the medium potential of the pair of common source lines and a relatively large parasitic capacity thereof, thereby maintaining the data lines at the half-precharge level. The pair of common source lines are shorted to each other during the non-select period of the memory arrays, so that the common source lines have a medium level which is substantially equal to the half-precharge level of the data lines.

This is a divisional of application Ser. No. 878,072, filed June 24,1986, now U.S. Pat. No. 4,780,852.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory and, moreparticularly, to a technique useful for a half-precharge type dynamicRAM (random-access memory).

In a dynamic RAM having a memory capacity, e.g., 1M bits, each of thememory cells has a relatively small size, and an exceedingly largenumber of memory cells are connected to each of the data lines. Inaccordance with these circumstances, the relationship between thecapacity Cs of the storage capacitor of each memory cell and thefloating capacity (data line capacity) Co of each data line, i.e., theratio Cs/Co, becomes an exceeding small value. In consequence, a datasignal applied to the data line from a memory cell, that is, a potentialchange applied to the data line in accordance with the amount of chargestored in the capacitor Cs, undesirably becomes an exceedingly minutevalue.

To overcome this problem, a dynamic RAM having the following arrangementis proposed in U.S. patent application Ser. No. 380,409, filed May 20,1982, Ito et al. According to this technique, in order to ensure adesired read level from each memory cell, each data line is divided intoa multiplicity of portions, that is, a memory array is divided into amultiplicity of regions in the direction of the data lines, therebyreducing the number of memory cells connected to each data line in eachof the divided memory array regions and thus maintaining the ratio Cs/Coat a desired value.

SUMMARY OF THE INVENTION

The present inventors have examined the following techniques for thepurpose of increasing the scale of integration of a dynamic RAM of thetype in which each data line is divided, of simplifying the arrangementof such RAM, and of lowering the power consumption thereof. First, toincrease the scale of integration, a common data line selecting signalline is employed, that is, a select signal for data lines in each of thedivided memory arrays is formed by a single column address decoder. Tosimplify the arrangement of the memory arrays and lower the powerconsumption, the half-precharge method (dummy-cellless method) isadopted. The half-precharge method is mentioned in ISSCC (IEEEInternational Solid-State Circuits Conference) 84 DIGEST OF TECHNICALPAPERS, p. 276 to p. 277. For lowering the power consumption, a senseamplifier in the one of the divided memory arrays in which a memory cellto be selected is present is operated alone.

The present inventors have found that the following problems arise whenthe above-described techniques are adopted. When a select signal forselecting one of the data lines in a plurality of divided memory arraysis formed by a common column address decoder, one data line in each ofthe non-selected memory arrays is undesirably connected to the commondata line. The data line holds the above-described half-precharge level,whereas the common data line has a potential higher than the potentialof the data line. Since the data line has a relatively small capacity Coas a result of the division of it, the potential of the data line isgreatly fluctuated by the connection with the common data line. Inconsequence, during the read operation from the selected memory cellconnected to the data line at the subsequent timing, level imbalance mayoccur between the pair of data lines, or the operating point of theassociated sense amplifier is biased to a low-sensitivity region,resulting in an erroneous read operation.

Accordingly, it is an object of the present invention to provide asemiconductor memory so designed that the scale of integration isincreased, and the operation is stabilized.

It is another object of the present invention to provide a dynamic RAMso designed that the scale of integration is increased, while the powerconsumption is lowered, and yet the operation is stabilized.

The above and other objects, novel features and advantages of thepresent invention will become clear from the following description ofthe preferred embodiment thereof, taken in conjunction with theaccompanying drawings.

A brief summary of a representative embodiment of the novel techniquesdisclosed in this application is as follows. Each of the common datalines in the nonselected ones in the divided memory arrays and a pair ofcommon source lines of the associated sense amplifier are connectedtogether. The pair of common source lines are shorted to each otherduring a nonselect period, so that they have a medium level which issubstantially the same as the half-precharge level of the data lines.Making use of the medium potential of the common source lines and arelatively large parasitic capacity thereof, the potential of the commondata line is set at a medium level which is substantially the same asthat of the data lines, whereby the data lines are maintained at thehalf-precharge level.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an essential part of the dynamic RAMaccording to the present invention;

FIG. 2 is a block diagram which schematically shows the generalarrangement of the dynamic RAM illustrated in FIG. 1; and

FIG. 3 is a timing chart showing one example of the operation of thedynamic RAM illustrated in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 and FIG. 2 show one principal embodiment of the dynamic RAMaccording to the present invention. The circuit elements shown in FIG. 1are formed on a semiconductor substrate, such as one which is made of asingle crystal silicon, by the semiconductor integrated circuittechnique, although this is not necessarily limitative.

The operations of the illustrated circuits, which constitute incombination a RAM, are respectively controlled by various timing signalsgenerated from a timing generating circuit TC as will be clear from theexplanation below.

As shown in FIG. 2, the dynamic RAM in accordance with this embodimenthas four memory arrays M-ARY1 to M-ARY4, although this is notnecessarily limitative. Each memory array is provided with a prechargecircuit PC, a sense amplifier SA, a column switch C-SW, a pair of commondata lines CD, a pull-up circuit L0D for the common data lines CD, aswitching circuit SW for half-precharging the common data lines CD, anda row (X).address decoder XDCR. A numeral which is suffixed to thereference symbol representing each of the circuits denotes a memoryarray M-ARY corresponding to this circuit. According to the presentinvention, a single column (Y) address decoder YDCR is provided incommon to all the four memory arrays M-ARY1 to M-ARY4.

The memory arrays and the circuit blocks respectively have the sameconfigurations as each other. Accordingly, two memory arrays M-ARY1 andM-ARY2 and the circuit blocks provided corresponding to them areexemplarily shown in FIG. 1 as representatives, and illustration of theother memory arrays and circuit blocks is omitted. As to the prechargecircuit and the sense amplifier, portions thereof which correspond tothe memory array M-ARY1 alone are shown in detail. In the followingdescription, only the memory array M-ARY1 and the circuits providedcorresponding thereto will be explained.

The memory array M-ARY1 is, as shown in FIG. 1, constructed of thefolded bit line (data line) system. Therefore, the memory array M-ARY1has a plurality of pairs of data lines, i.e., a plurality ofcomplementary data lines D, {overscore (D)} a plurality of dynamicmemory cells each connected at the input/output terminal thereof to thecorresponding data line, and a plurality of word lines W to which areconnected the respective select terminals of the corresponding dynamicmemory cells. The memory cells are respectively disposed at theintersections between one pair of data lines D, {overscore (D)}0 and oneword line W, which are exemplarily shown.

Each of the 1-bit memory cells MC is, as illustrated, constituted by adata storage capacitor Cs and an N-channel MOSFET Qm for addressselection. The data which is represented by the logics “1” and “0” isstored in the form of the presence and absence of electric charge in thecapacitor Cs, respectively. The data is read out in such a manner that,with the MOSFET Qm turned ON, the capacitor Cs is connected to eitherone of the complementary data lines, and a change in the potential ofthe data line in accordance with the amount of charge accumulated in thecapacitor Cs is sensed.

In this embodiment, despite that the number of memory cells in thedirection of data lines is increased, the number of memory cellsconnected to each pair of complementary data lines is made relativelysmall by dividing the memory array into a multiplicity of memory arrayregions such as the memory arrays M-ARY1 to M-ARY4. As a result, theratio between the capacity of the capacitor Cs and the floating capacityCo (not shown) of the data line to which the capacitor Cs is connectedhas a desired value which enables a minute read signal correspondingthereto to be satisfactorily discriminated by the sense amplifier SA(described below).

To form a reference potential for the sensing operation of the senseamplifier SA for detecting such minute signal, the half-precharge methodis utilized in this embodiment. For this purpose, a precharge circuitPC1 which is composed of N-channel MOSFETs Q25, Q26 and Q27 is provided.The MOSFET Q25 shorts the complementary data lines D, {overscore (D)}0which are respectively brought to a high level (Vcc) and a low level (0V) by the amplifying operation of the sense amplifier SA1 during aperiod in which the sense amplifier SA1 is in an inoperative state. Inconsequence, a precharge voltage of about Vcc/2 is given to each of thecomplementary data lines D, {overscore (D)} The MOSFETs Q26 and Q27 areprovided in order to prevent possible fluctuations in the half-prechargelevel of the complementary data lines due to, for example, a bump of thesupply voltage Vcc during the amplifying operation of the senseamplifier SA1. A precharge voltage of about Vcc/2, which is obtained asa result of shorting between a pair of common source lines NS1 and PS1(described below) which have a relatively large capacity, is suppliedthrough the MOSFETs Q26 and Q27. In this way, the precharge level of thecomplementary data lines D, {overscore (D)}0 can stably be maintained atabout Vcc/2. This is effective in increasing the read margin and alsoincreasing the read speed. A row timing signal RAS2 is supplied to therespective gates of the MOSFETs Q25, Q26 and Q27, although this is notnecessarily limitative.

Each of the unit circuits USA which constitute in combination the senseamplifier SA1 is defined by a CMOS latch circuit in which two CMOSinverter circuits are respectively formed from P-channel MOSFETs Q30,Q32 and N-channel MOSFETs Q31, Q33, and the respective input and outputterminals of these CMOS inverter circuits are cross-coupled to eachother. A pair of input and output terminals of this CMOS latch circuitare respectively connected to the corresponding complementary data linesD, {overscore (D)} The respective sources of the P-channel MOSFETs Q30,Q32 are connected in common to those of the other unit circuits USAwhich are provided in the same memory array M-ARY1, thereby forming acommon source line PS1. The respective sources of the N-channel MOSFETsQ31, Q33 are connected in common to those of the other unit circuits USAin the same memory array M-ARY1, thereby forming a common source lineNS1.

The common source line PS1 is supplied with the supply voltage Vccthrough a P-channel MOSFET Q15, while the common source line NS1 issupplied with the circuit ground potential through an N-channel MOSFETQ16. When a memory cell in the memory array M-ARY1 is selected in anoperating cycle, complementary timing signals φpa1 and φpa1 whichactivate the sense amplifier SA1 are applied to the respective gates ofthe power switch MOSFETs Q15 and Q16. In consequence, the senseamplifier SA1 effects an operation in which a minute read signal whichis given to either one of the complementary data lines from the selectedmemory call is differentially amplified on the basis of a referencevoltage which is defined by the half-precharge voltage applied to theother complementary data line. If no memory cell in the memory arrayM-ARY1 is selected in the memory operating cycle, the timing signalsφpa1 and φpa1 are not generated, and the MOSFETs Q15 and Q16 areconsequently allowed to remain OFF. A P-channel MOSFET Q17 for shortingis provided between the pair of common source lines PS1 and NS1 of thesense amplifier SA1. When the sense amplifier SA1 is in an inoperativestate, the common source lines PS1 and NS1 are shorted to each other bythe operation of the P-channel MOSFET Q17, so that the potential of thecommon source lines PS1 and NS1 becomes about Vcc/2. As a result, theamplifying MOSFETs Q30 to Q33 and the like in the unit circuits USA caninfallibly be turned OFF, and it is therefore possible to prevent therespective high and low levels of the complementary data lines D and{overscore (D)}0 before the precharging operation from being undesirablyfluctuated by the change in level of the common source lines PS1 andNS1.

The row (X) address decoders XDCR1 to XDCR4 and the column (Y) addressdecoder YDCR are respectively supplied with internal complementaryaddress signals ax0 to axn-2 and ay0 to ayn which are formed by addressbuffers XADB and YADB. The row address buffer XADB fetches external rowaddress signals AX0 to AXn in response to the operation of the timinggenerating circuit TC which generates a timing signal for controllingthe fetching of address signals in synchronism with the generation of arow address strobe signal {overscore (RAS)} although this is notnecessarily limitative. As a result, row internal complementary addresssignals ax0 to axn-2 which are to be supplied to the row addressdecoders XDCR1 to XDCR4 are output from the above-described addressbuffers. The column address buffer YADB fetches external column addresssignals AY0 to AYn in response to the generation of a similar timingsignal in synchronism with the generation of a column address strobesignal CAS, and outputs column internal complementary address signalsay0 to ayn which are to be supplied to the column address decoder YDCR.These multi-address type address buffers may be formed by utilizingaddress buffer circuits in accordance with well-known dynamic RAMtechnology.

Internal complementary address signals axn-1 and axn which respectivelycorrespond to the two high-order bits AXn-1 and AXn in the external rowaddress signals are supplied to a decoder DEC. The decoder DEC decodesthese two-bit signals to output signals X00, X01, X10 and X11. Thesignals X00 to X11, which are selectively raised to the high level, areemployed to select one of the four memory arrays M-ARY1 to M-ARY4 andthe circuits corresponding to the selected memory array. For thispurpose, the signals X00 to X11 are supplied to the timing generatingcircuit TC and the switching circuits SW. For example, when the signalX00 is at the high level, the memory array M-ARY1 and the circuits whichcorrespond to this memory array are selected. The timing generatingcircuit TC generates signals φx1 to φx4 and φpal to φpa4 whichcorrespond to the signals X00 to X11. The signals φx1 to φx4 and φpa1 toφpa4 are alternatively raised to the high level in correspondence withthe signals X00 to X11.

The row address decoders XDCR1 to XDCR4 are laid out below therespective memory arrays M-ARY1 to M-ARY4 as viewed in FIG. 1. Theoutput terminals of the row address decoders XDCR1 to XDCR4 arerespectively connected to the word lines W in the corresponding memoryarrays. The operations of these row address decoders XDCR1 to XDCR4 arerespectively controlled by word line selecting timing signals φx1 to φx4generated from the timing generating circuit TC, so as to output wordline selecting signals in synchronism with these timing signals,respectively. In this case, one of the four row address decoders XDCR1to XDCR4 outputs a signal for selecting one word line, and the otherthree row address decoders output no word line selecting signal. Inother words, the three row address decoders are made inoperative by thecorresponding timing signals φx1 to φx4. Accordingly, one word line inone of the memory arrays M-ARY1 to M-ARY4 is selected, while the wordlines in the other three memory arrays remain non-selected. Since therow address decoders XDCR1 to XDCR4 can be formed by utilizing a knownaddress decoder circuit, the details thereof are not illustrated; eachrow address decoder is constituted by a plurality of unit circuits whichoutput signals to the word lines, respectively, in the correspondingmemory arrays M-ARY1 to M-ARY4.

The operation of the column address decoder YDCR is controlled by a dataline selecting timing signal output from the timing generating circuitTC or a column selection timing signal φy, so as to output a data lineselecting signal or a column selecting signal in synchronism with thecontrol timing signal. The column address decoder YDCR is laid out onthe right-hand side of the memory arrays as illustrated, although thisis not necessarily limitative. An exemplarily shown output line of thecolumn address decoder YDCR, i.e., a data line select line YS1, extendsover the memory arrays so as to be connected in common to the respectivegates of switching MOSFETs (e.g., Q2, Q3) which constitute therespective column switches C-SW1 to C-SW4 of the memory arrays M-ARY1 toM-ARY4. Each of the data line select lines YS is provided so as tocorrespond to a pair of complementary data lines, although this is notnecessarily limitative. Since the column address decoder YDCR can beformed by utilizing a known address decoder circuit, the details thereofare not illustrated; it is constituted by a plurality of unit circuitswhich respectively supply their outputs to the data line select lines.Each of the unit circuits is composed of, for example, a known CMOSstatic NAND gate circuit and a known CMOS inverter circuit.

Each of the unit circuits which constitute in combination the columnswitch C-SW1 is, as exemplarily shown, provided between a pair of commoncomplementary data lines CD1, {overscore (CD1)}0 (CD2, {overscore (CD2)}and each pair of complementary data lines D, {overscore (D)}0 in thememory array M-ARY1 (M-ARY2). Each unit circuit is composed of N-channelswitching MOSFETs Q2, Q3 (Q5, Q6) which are supplied with a common dataline select signal formed by the column address decoder YDCR.

In accordance with this embodiment, the respective column switches C-SW1to C-SW4 of a total of four memory arrays M-ARY1 to M-ARY4 are suppliedwith the output signal from the common column address decoder YDCR,whereby it is possible to simplify the circuit configuration.

In accordance with this embodiment, on the other hand, the operations ofthe row address decoders XDCR1 to XDCR4 and the corresponding senseamplifiers SA1 to SA4 for the memory arrays M-ARY1 to M-ARY4 areselectively effected in response to the signals φx1 to φx4 and φpa1 toφpa4 generated in correspondence with the row address signals axn-1,axn. Therefore, the timing generating circuit TC is adapted to receivesome bits axn-1, axn in the row internal complementary address signalsoutput from the address buffers and to selectively generate the timingsignals φx1 to φx4 and φpa1 to φpa4 (high level) required for theoperations of the above-described circuits on the basis of the inputinternal complementary address signals.

In this embodiment, only a word line in a memory array which includes amemory cell to be selected is brought into a select condition in thememory access state, and only the sense amplifier corresponding to thatmemory array is made operative. In consequence, any unnecessary wordline selecting operation and sense amplifier operation in the remainingmemory arrays are not conducted to lower the power consumption. However,the employment of the common column address decoder YDCR involves thefollowing problem. When the selected data line in the selected memoryarray is connected to the corresponding common data line, thecomplementary data lines in the remaining, non-selected, memory arraysare undesirably connected to the corresponding common data lines at thesame time. There are cases where the potential of the common data linescorresponding to the non-selected memory arrays is different from thehalf-precharge potential of the complementary data lines as a result of,for example, the read or write operation in the previous cycle, or abump of the supply voltage. In such cases, the half-precharge potentialof the data lines in the memory arrays is disadvantageously raised bythe operation of the column switches.

Accordingly, in this embodiment, the potential of the common data linesCD, {overscore (CD)}0 in each of the non-selected memory arrays are madesubstantially equal to the half-precharge level by utilizing thefloating capacity and holding potential, which are set at relativelylarge values, of the common source lines PS and NS of the senseamplifiers. For this purpose, a switching circuit SW1 is provided whichis composed of P-channel MOSFETs Q17 to Q19, a gate circuit G3 and aninverter circuit IV3. P-channel switch MOSFETs Q18 and Q19 are providedbetween the common data lines CD1, {overscore (CD1)}0 and the commonsource lines PS1, NS1 of the corresponding sense amplifier SA1. SimilarP-channel MOSFETs Q23, Q24 are provided between another pair of commondata lines CD2, {overscore (CD2)}0 and the common source lines PS2, NS2of the corresponding sense amplifier SA2, which are also exemplarilyshown.

The respective gates of the MOSFETs Q18, Q19 are connected in common tothe gate of the P-channel MOSFET Q17 which is adapted to short thecommon source lines PS1 and NS1, and supplied with a select signal c1which is formed by a logic circuit composed of a CMOS NAND gate circuitG3 which receives a row timing signal RAS1 and a signal X00 fordesignating the memory array M-ARY1, and a CMOS inverter circuit IV3.

The respective gates of MOSFETs Q23, Q24 of a switching circuit SW2which corresponds to the common data lines CD2, {overscore (CD2)}0 areconnected in common to the gate of a P-channel MOSFET Q22 which isadapted to short the common source lines PS2 and NS2, and supplied witha select signal c2 which is formed by a logic circuit composed of a NANDgate circuit G4, similar to the above, which receives the timing signalRAS1 and a signal X01 for designating the memory array M-ARY2, and aCMOS inverter circuit IV4.

Switching circuits SW3 and SW4 which respectively connect the commondata lines and the common source lines corresponding to the other memoryarrays M-ARY3 and M-ARY4 are also controlled by respective outputsignals of logic circuits similar to the above. However, the logiccircuits of the switching circuits SW3 and SW4 are respectively suppliedwith outputs X10 and X11 (not shown) of the decoder circuit DEC whichrespectively designate the memory arrays M-ARY3 and M-ARY4.

In this embodiment, a pull-up circuit LOD is provided at one end of eachpair of common data lines for the purpose of increasing the read speed,although this is not necessarily limitative. A pull-up circuit LOD1which corresponds to the common data lines CD1, {overscore (CD1)}0 iscomposed of N-channel MOSFETs Q7 to Q10, a CMOS inverter circuit IV1 anda CMOS NAND gate circuit G1. The common data lines CD1, {overscore(CD1)}0 are provided with load (pull-up) MOSFETs Q7, Q8. The respectivegates of the load MOSFETs Q7, Q8 are supplied with the output signalfrom an inverter circuit IV1 which inverts the output signal of a NANDgate circuit G1 which receives a select signal c1 for the memory arrayM-ARY1 and a read/write control signal rwc. MOSFETs Q11, Q12 which areprovided for another pair of common data lines CD2, {overscore (CD2)}0are also supplied with the output signal from a gate circuit composed ofa gate circuit G2 and a CMOS inverter circuit IV2, which are similar tothose described above. N-channel MOSFETs Q9, Q10 which pass a very smallcurrent are respectively provided between the common data lines CD1,{overscore (CD1)}0 and the circuit ground potential point. Therespective gates of the MOSFETs Q9, Q10 are connected in common to thegates of the MOSFETs Q7, Q8. Another pair of common data lines CD2,{overscore (CD2)}0 are also provided with MOSFETs Q13, Q14 which aresimilar to the those described above.

The pull-up circuit LOD1 is adapted to raise the potential of the commondata lines CD1 and {overscore (CD1)}0 from the half-precharge level to apredetermined high voltage when a read operation is started in responseto the rise of the signal rwc to a high level and the memory arrayM-ARY1 is selected in response to the rise of the signal C1 to a highlevel. This predetermined potential is, for example. Vcc-Vth (Vthrepresents the threshold voltage of the MOSFETs 7, Q8). The potential ofthe common data lines CD1, {overscore (CD1)}0 changes in accordance withthe potential of the complementary data lines which are connected afterthe above-described pull up operation. The potential of the common datalines which are connected to the data lines at the high level hassubstantially no change. The potential of the common data lines whichare connected to the data lines at the low level is dropped from thepotential Vcc-Vth toward the ground potential by the operation of thesense amplifier SA1 (or the MOSFET Q31 or Q33) which is connected to thecommon data lines through the column switch C-SW1.

The provision of the pull-up circuit LOD1 enables column addresses aloneto be changed without any change of row addresses, thereby allowing ahigh-speed operation (e.g., the column static operation) of reading outdata stored in another memory cell MC. More specifically, the provisionof the pull-up circuit LOD1 eliminates the need to precharge the commondata lines CD1, {overscore (CD1)}0 prior to a subsequent operation ofreading out the data stored in another memory cell MC. In addition, theamplitude of the common data line CD1 or {overscore (CD1)}0 is reducedor limited by the combination of the MOSFETs Q7 and Q9 or the MOSFETs Q8and Q10. Since the column address buffer YADB and the column decoderYDCR are respectively constituted by static circuits, column address arecontinuously changed over from one to another at high speed. Since thecommon data lines CD1, {overscore (CD1)}0 perform a kind of staticoperation by virtue of the provision of the pull-up circuit LOD1, datacan be continuously read out at high speed.

After data has been read out, the respective potentials of the commondata lines CD1, {overscore (CD1)}0 are changed to a high level and a lowlevel, respectively. This high level may be made higher than the supplyvoltage Vcc by a bump of the supply voltage Vcc of the pull-up circuitLOD1. However, both the common data lines CD1, {overscore (CD1)}0 are,thereafter, respectively shorted to the common source lines PS1 and NS1having a relatively large wiring capacity during the nonselect period ofthe memory array M-ARY1. In consequence, the above-described high-levelpotential is made substantially equal to the half-precharge level of thedata lines. In other words, it is possible to prevent destruction of thehalf-precharge level of the complementary data lines due to possiblenoise which may be generated in the pull-up circuit LOD1.

In this embodiment, during the non-select period of the memory arrayM-ARY1 the MOSFETs Q26 and Q27 turn ON in response to the rise of thesignal {overscore (RAS2)}0 to a high level and the MOSFETs Q17 to Q19turn ON in response to the fall of the signal C1 to a low level as aresult of the shift of the signal X00 to a low level, although this isnot necessarily limitative. More specifically, all the complementarydata lines D, {overscore (D)}0 in the memory array M-ARY1, the commonsource lines PS1, NS1 and the common data lines CD1, {overscore (CD1)}0are shorted to each other. Thus, the potential of the common data lineCD1, {overscore (CD1)}0 can be made substantially equal to thehalf-precharge level even more stably. In addition, the potential of thecommon data lines CD1, {overscore (CD1)}0 can be made equal to thepotential of all the complementary data lines D, {overscore (D)}0 in thememory array M-ARY1.

The common data lines CD1, {overscore (CD1)}0 are connected to inputterminals of a main amplifier MA1 and output terminals of a data inputbuffer DIB, although this is not necessarily limitative. The mainamplifier MA1 is constituted by a CMOS circuit which is similar to thatof the sense amplifier SA1, and the output signal from the mainamplifier MA1 is delivered to an external terminal through a data outputbuffer DOB.

The operation of the data input buffer DIB is controlled by a timingsignal generated from the timing generating circuit TC, so as to form awrite signal corresponding to a write signal supplied thereto from anexternal terminal Din and supply it to the corresponding common datalines CD1, {overscore (CD1)} The data input buffer DIB, when placed inan inoperative state, exhibits high-output impedance characteristics.

Similarly, the operations of the main amplifier MA1 and the data outputbuffer DOB are controlled by a timing signal generated from the timinggenerating circuit TC, so as to receive a signal read out from thecorresponding common data lines CD1, {overscore (CD1)}0 and amplify aswell as deliver the signal to the external terminal Dout.

The timing generating circuit TC for controlling the operations ofreading and writing data receives a row address strobe signal {overscore(RAS)} a column address strobe signal {overscore (CAS)}0 and a writeenable signal {overscore (WE)}0 which are supplied thereto from externalterminals {overscore (RAS)} {overscore (CAS)}0 and {overscore (WE)}respectively, and forms various timing signals (e.g., RAS1, {overscore(RAS2)} rwc, etc.) on the basis of the input signals.

The operation of this embodiment will be schematically explained belowwith reference to a timing chart shown in FIG. 3. It should be notedthat FIG. 3 shows a timing chart related to the memory arrays M-ARY1 andM-ARY2.

In a stand-by state, the row address strobe signal {overscore (RAS)}0and the column address strobe signal {overscore (CAS)}0 are raised tohigh levels, respectively, such as those shown in FIG. 3. In response tothis, the timing generating circuit TC shifts the internal signals RAS1and {overscore (RAS2)}0 to a low level and a high level, respectively,and brings the various internal timings signals rwc, φpa, φx and φy intoa reset state which is a low level. In response to the shift of thesignal RAS1 to the low level, the signals c1 to c4 are shifted to a lowlevel, and this causes the pull-up circuits LOD1 to LOD4 to be broughtinto an inoperative state and also causes the MOSFETs Q17 to Q19, Q22 toQ24, etc. in the switching circuits SW1 to SW4 to turn ON. In responseto the shift of the signal φpa to the low level (the shift of the signalφpa to the high level), the MOSFETs Q15, Q16, Q20, Q21, etc. are turnedOFF, and this causes the outputs of all the sense amplifiers SA1 to SA4to be brought into a high-impedance state, so that the complementarydata lines, which are connected to these sense amplifiers SA1 to SA4,are also brought into a high-impedance (floating) state. In response tothe rise of the internal signal {overscore (RAS2)}0 to the high level,the precharge MOSFETs Q25 and the like in the precharge circuit PC1 toPC4 are turned ON so as to short the complementary data lines D,{overscore (D)}0 which are at high and low levels, respectively, as aresult of the amplifying operation of the corresponding sense amplifiersin the previous memory operating cycle, thus effecting ahalf-precharging operation. When the MOSFETs Q17, Q22, etc. in theswitching circuits SW1 to SW4 are turned ON, the common source linesPS1, NS1 and PS2, NS2 are respectively shorted to each other. Thus, thesupply voltage Vcc supplied to either one of the common source lines inthe previous operating cycle and the ground potential of the othercommon source line are averaged to obtain a potential which issubstantially equal to Vcc/2, i.e., a half voltage. When the MOSFETsQ18, Q19 and Q23, Q24, etc. in the switching circuits SW1 to SW4 areturned ON, the common source lines PS1, NS1 and PS2, NS2 and the commondata lines CD1, {overscore (CD1)}0 and CD2, {overscore (CD2)}0 arerespectively shorted to each other. Since the respective sources of amultiplicity of amplifying MOSFETs constituting the sense amplifier SAare connected in common to the common source lines PS and NS, thesecommon source lines have a relatively large floating capacity.Accordingly, the potential of the common data lines CD1, {overscore(CD1)} etc. which are respectively connected to the common source linesPS1 and NS1 is made coincident with the above-described half potential.In response to the rise of the signal {overscore (RAS2)}0 to the highlevel, further, the MOSFETs Q26, Q27, etc. in the precharge circuits PC1to PC4 are turned ON. The half voltage, which is obtained by shortingthe common source lines, is also applied to the complementary data linesin the memory arrays M-ARY1 to M-ARY4. In consequence, even when thehalf-precharge level of the complementary data lines obtained as aresult of the turning-on of the MOSFETs Q25 and the like is offset fromVcc/2, the offset level can be corrected to a potential which issubstantially equal to Vcc/2.

The access to the RAM is started in response to the fall to a low levelof the row address strobe signal {overscore (RAS)}0 which is practicallya chip select signal. In synchronism with the fall of the signal{overscore (RAS)} the timing generating circuit TC shifts the signalsRAS1 and {overscore (RAS2)}0 to a high level and a low level,respectively. In response to the shift of the precharging timing signal{overscore (RAS2)}0 to the low level, the precharge circuits PC1 to PC4are made inoperative.

The row address buffer XADB fetches as a row address signal X1 theaddress signals AX0 to AXn which are supplied from an external terminalin response to the rise to a high level of the timing signal RAS1generated from the timing generating circuit TC. The internalcomplementary address signals axn-1 and axn which respectivelycorrespond to the two high-order bits AXn-1 and AXn in the addresssignals AX0 to AXn are delivered to the decoder DEC, and the remaininginternal complementary address signals ax0 to axn-2 are respectivelydelivered to the row address decoders XDCR1 to XDCR4. The decoder DEC,which is operated at substantially the same timing as the signal RAS1,decodes the signals axn-1 and axn and forms memory array selectingsignals X00 to X11. For example, the memory array M-ARY1 is selected inresponse to the rise of the signal X00 to a high level. When the signalsX00 and RAS1 are raised to a high level, the signal c1 alone is raisedto a high level, and the MOSFETs Q17 to Q19 alone are turned OFF. Sincethe signals X01 to X11 are held the low level, the signals c2 to c4 areheld at the low level. In response to the rise of the signal X00 to thehigh level, the timing generating circuit TC raises only a word lineselecting timing signal φx1 (not shown) to a high level which has beenbrought to a reset level, that is, a low level, in advance during thestand-by period of the RAM. In response to the rise of the word lineselecting timing signal φx1 to the high level, the row address decoderXDCR1, which corresponds to the memory array M-ARY1 including a memorycell designated by the address signal X1, is activated to decode theabove-described signal and raise one word line W to a high level so asto be brought into a selective state. At this time, in response to theall of the signals φx2 to φx4 to the low level, the row decoders XDCR2to XDCR4 are made inoperative. Accordingly, all the word lines innon-selected memory arrays such as the memory arrays M-ARY2 to M-ARY4are held in the reset state of low level.

As a result of this selecting operation, either one of the complementarydata lines D, {overscore (D)}0 in the memory array M-ARY1 has a minuteread signal in accordance with the charge (the logic “0” in thisembodiment) held in the data storage capacitor Cs in the selected memorycell MC, and the other data line maintains the half-precharge level. Inconsequence, a minute potential difference in accordance with the datastored in the memory cell MC is produced between the complementary datalines D, {overscore (D)} In response to the rise of the signal c1 to ahigh level, the switching MOSFETs Q18, Q19 for connecting the commonsource lines PS1, NS1 of the sense amplifier SA1 provided for the memoryarray M-ARY1 to be selected and the common data lines CD1, {overscore(CD1)} together with the switching MOSFET Q17 for shorting the commonsource lines PS1 and NS1, are turned OFF.

The timing signals φpa1, φpa1 for activating the sense amplifier SA1provided for the memory array M-ARY1 are shifted to a high level and alow level, respectively, after the word line W has been shifted to theselect level. More specifically, the timing generating circuit TC shiftsonly the signal φpa1 to a high level (the signal φpa1 to a low level) inresponse to the rise of the signal X00 to the high level which takesplace after an appropriate period of time has elapsed from the time ofthe rise of the signal φx1 to the high level. The signals φpa2 to φpa4are maintained at the low level because of the low level of the signalsX01 to X11. In consequence, the power switch MOSFETs Q15 and Q16 whichrespectively supply operating voltages (Vcc and the circuit groundpotential) to the sense amplifier SA1 are turned ON, and the amplifyingoperation of the sense amplifier SA1 is thereby started. The leveldifference, which is given between the complementary data lines in thememory array M-ARY1 from the selected memory cell MC, is eventuallyamplified to a level such as a high level or a low level.

After an appropriate period of time has elapsed from the time of thefall of the signal {overscore (RAS)}0 to the low level, the columnaddress strobe signal {overscore (CAS)}0 is brought to a select level,that is, a low level. As a result, the timing generating circuit TCfirst generates a timing signal for the column address buffer YADB. Inconsequence, the address buffer YADB fetches as the column addresssignal Y1 address signal AY0 to AYn supplied from an external terminaland outputs internal complementary address signals ay0 to ayncorresponding to the supplied address signals. Then, a data lineselecting timing signal φy (not shown) is output from the timinggenerating circuit TC. The column address decoder YDCR is activated inresponse to the data line selecting timing signal φy so as to decode theinternal complementary address signals, thereby forming a data lineselecting signal. When a high level signal is output from the columnaddress decoder YDCR to, for example, the data line selecting line YS1,a pair of complementary data lines in each of the memory arrays M-ARY1to M-ARY4 are respectively connected to the corresponding one of thepairs of common data lines CD1, {overscore (CD1)}0 to CD4, {overscore(CD4)} In the memory arrays M-ARY2 to M-ARY4 which are in anon-selective state at this time, the potential of the common data linesCD2, CD2 to CD4, CD4 is made substantially equal to the half-prechargepotential by the connection between the common data lines and the commonsource lines of the corresponding sense amplifiers which takes place inresponse to the fall of the signals c2 to c4 to the low level.Accordingly, even when the data lines and the common data lines in thenon-selected memory arrays are connected in response to theabove-described common data line selecting signal each of the data linesmaintains a potential substantially equal to the half-precharge level.Thereafter, the read/write signal rwc is generated. More specifically,if the write enable signal {overscore (WE)}0 is at a high level whichrepresents a read operation, the timing generating circuit TC raises thesignal rwc to a high level and then raises a main amplifier operationtiming signal φma to a high level a little after the rise of the signalrwc. In consequence, the signal read out to the common data lines CD1,{overscore (CD1)}0 is amplified by the main amplifier MA1, and a readsignal D1 is delivered to an external terminal through the data outputbuffer DOB. At this time, because of the high level of the signal c1 andthe rise of the control signal rwc to the high level, the pull-upMOSFETs Q7 to Q10 for the common data lines CD1, {overscore (CD1)}0 areturned ON. In other words, the pull-up circuit LOD1 is made operative.The other pull-up circuits LOD2 to LOD4 remain inoperative because ofthe low level of the signals c2 to c4. In consequence, the potential ofthe common data lines CD1, {overscore (CD1)}0 is raised from thehalf-precharge level to a potential Vcc-Vth and further amplified inaccordance with the potential of the complementary data lines. On theother hand, when the write enable signal {overscore (WE)}0 is at a lowlevel which represents a write operation, the timing generating circuitTC generates a timing signal for activating the data input buffer DIB.In this case, the control signal rwc is shifted to the low level, andthe pull-up circuits LOD1 to LOD4 are made inoperative. The write datasignal from the external terminal D is supplied to the complementarydata line in the memory array M-ARY1 through the data input buffer DIB,the common data lines CD1, {overscore (CD1)}0 and the column switchC-SW1, whereby data is written into the selected memory cell MC.

When the row address strobe signal {overscore (RAS)}0 is raised to thehigh level, the RAM is brought into a stand-by state.

In this stand-by state, the word lines W in the selected memory arrayM-ARY1 are reset, and the sense amplifier SA1 is made inoperative. Whenthe timing signal {overscore (RAS2)}0 is raised to the high levelthereafter, the complementary data lines D, {overscore (D)}0 which areat the high and low levels, respectively, are shorted to each other soas to have a half-precharge potential.

Then, the row address strobe signal {overscore (RAS)}0 is shifted to thelow level again, and a row address signal X2 which is supplied insynchronism with the fall of the signal {overscore (RAS)}0 designates amemory cell-in, for example, the memory array M-ARY2. In consequence,one word lines W in the memory array M-ARY2 is selected, and the senseamplifier SA2 is made operative by an operation similar to the above. Inresponse to the fall of the column address strobe signal {overscore(CAS)}0 to the low level, a column selecting operation is conducted in amanner similar to the above.

In this embodiment, at least the column decoder YDCR is constituted by astatic circuit, and it is therefore possible to effect a column staticoperation. After a signal D2 read out from one memory cell MC designatedby the address signal Y2 has been delivered to the external terminal,this signal Y2 is changed over to a column address signal Y2′ withoutany change of the row address. In consequence, the column switches arechanged over from one to another, and a signal D2′ read out from amemory cell MC connected to a data line designated by the address signalY2′ is delivered to the external terminal. In order to realize suchcolumn static mode, the pull-up circuits LOD1 to LOD4 are needed. Morespecifically, since the previous read or write signal, which is at thelow level, is brought to the high level by the pull-up circuits LOD1 toLOD4 without any precharging operation, it is possible to form a read orwrite signal which is opposite in phase to the previous read or writesignal. Such continuous access mode enables realization of a high-speedoperation of the RAM.

The present invention offers the following advantages.

(1) Since a switching circuit is provided which connects the common datalines corresponding to each of the non-selected ones among the dividedmemory arrays to the common source lines of the corresponding senseamplifier, the potential of the common data lines can be madesubstantially equal to the half-precharge level of the data lines in thememory array. Accordingly, one column address decoder can be mutuallyused for all the divided memory arrays, so that it is possible toincrease the scale of integration.

(2) By virtue of (1), it is possible to provide a pull-up circuit forthe common data lines in order to realize a high-speed continuous accesssuch as a static column mode or a page mode.

(3) By virtue of (1), only a memory array which includes a memory cellto be selected is made operative in a memory access cycle, and the othermemory arrays are not selected, whereby it is possible to lower thepower consumption.

(4) By virtue of (1), a memory array can be divided into a plurality ofregions in the direction of the data lines. It is therefore possible toreduce the number of memory cells connected to each of the data lines.In consequence, the floating capacity of the data lines can bedecreased, and it is therefore possible to further reduce the size ofeach of the elements which constitute memory cells for the purpose ofincreasing the storage capacity. Accordingly, a dynamic RAM with anincreased scale of integration and an increased storage capacity can berealized in conjunction with the advantageous effect mentioned in (1).

(5) Since the half-precharge method can be adopted by virtue of (1), itbecomes unnecessary to provide any dummy cell, and this enables anincrease in the scale of integration. In addition, since it is notnecessary to consider deterioration of the read level margin due toimbalance between an element which constitutes each memory cell and anelement which constitutes each dummy cell, the operating margin can beincreased.

Although the invention accomplished by the present inventors has beendescribed in detail by way of one embodiment, it is a matter of coursethat the present invention is not necessarily limited to theabove-described embodiment and various changes and modifications may beimparted thereto without departing from the gist of the invention.

The arrangement may be such that a first timing signal and a secondtiming signal which is generated after the first timing signal areemployed in place of the timing signal φpa, and a power switch MOSFEThaving a relatively small conductance is turned ON in response to thefirst timing signal so as to activate each of the unit circuits, therebyeffecting an amplifying operation in a first stage, and then, a powerswitch having a relatively large conductance is turned ON in response tothe second timing signal to effect an amplifying operation in a secondstage.

The MOSFETs Q26 and Q27 in the precharge circuit may be omitted.Conversely, the MOSFET Q25 in the precharge circuit may be omitted.Alternatively, a potential Vcc/2 which is generated by an appropriateconstant-voltage generating circuit may be supplied to the node betweenthe MOSFETs Q26 and Q27. In this case also, the MOSFET Q25 may beomitted. This constant-voltage generating circuit may be adapted tosupply the above-described voltage by means of a precharge MOSFET whichis controlled by an appropriate constant voltage.

The circuit which supplies a precharge voltage of a substantially mediumlevel to the common data lines in each of the memory arrays and thecommon source lines of each sense amplifier may also be constituted byan appropriate constant-voltage generating circuit in addition to acircuit which shorts the lines which are at a high-level potential and alow-level potential, respectively.

The number of divided memory arrays is not necessarily limited to 4.Memory arrays may be laid out on both sides of the column decoder YDCR.It is possible to provide a plurality of column decoders and divide amemory array corresponding to each of the column decoders into aplurality of memory array regions in accordance with the presentinvention. The layout of a column decoder and memory arrays may bevariously modified.

For example, if it is necessary to reduce the refreshing cycle in thecase where a memory array is divided into four, a pair of divided memoryarrays (e.g., M-ARY1 and M-ARY3) and the corresponding sense amplifiersand the like may be selected. In such case, when two memory arrays(sense amplifiers) are selected in a manner similar to the above, theremaining two memory arrays (sense amplifiers) are left non-selected ina manner similar to the above. In this ease, a selector circuit is addedfor realizing a data input/output operation carried out on a bitwisebasis. For example, data is input to and output from the memory wayM-ARY1 alone by the operation of the selector circuit, while the memoryarray M-ARY3 is refreshed by the operation of the sense amplifier.

The present invention may also be applied to a dynamic RAM of the typein which a row address signal and a column address signal are suppliedfrom external address terminals which are independent of each other.

The present invention may be applied to any type of dynamic RAM otherthan those described above. Further, dynamic RAMs are not necessarilylimitative, and the present invention may be widely applied tosemiconductor memories. The present invention may be effectively appliedto a semiconductor memory in which a memory array is divided, and acolumn decoder is provided in common with respect to the divided memoryarrays. Even in an arrangement where data lines are not constituted bycomplementary data lines, or the half-precharge method is not adopted,if the arrangement involves the problem that the potential of the datalines and that of the common data lines are made different from eachother, the present invention is effective in making these potentialsequal to each other. The present invention is particularly effective inan arrangement adopting the half-precharge method.

We claim:
 1. A semiconductor memory comprising: a plurality of memoryarrays each including pairs of data lines, word lines intersecting saidpairs of data lines, and memory cells respectively provided at theintersections between said pairs of data lines and said word lines,wherein each of said memory cells includes a MOSFET and a capacitorcoupled to said MOSFET for storing data; precharge means for prechargingsaid pairs of data lines to a potential which is substantially mediumbetween first and second potentials; pairs of common data lines providedrespectively corresponding to said memory arrays; first switching meansfor connecting each of said pairs of common data lines to each of saidpairs of data lines in the memory array which said switching circuitrespectively corresponds to; a plurality of word selecting meansprovided respectively corresponding to said memory arrays, wherein eachof said word selecting means selects one of said word lines; columnselecting means provided in common with respect to said memory arrays,said column selecting means including means for connecting each of saidpairs of common data lines respectively to one pair of data linesselected from among said pairs of data lines in each of said memoryarrays by means of said switching means on the basis of a common columnselecting signal; memory array selecting means for selecting one of saidplurality of memory arrays so that a memory cell is selected by therespective operation of said column selecting means, said plurality ofword selecting means, and said memory array selecting means; and voltagesupply means for supplying a potential having a substantially identicalpotential to said medium potential to a pair of common data linescorresponding to a memory array which is not selected by said memoryarray selecting means when said memory array selecting means selects oneof said memory arrays.
 2. A semiconductor memory according to claim 1,further comprising: a plurality of sense amplifiers, wherein each ofsaid sense amplifiers corresponds respectively to a predetermined pairof data lines, said sense amplifiers including means for amplifying alevel difference between a reference potential corresponding to saidmedium potential precharged on one of said pair of said data lines and adata potential applied to another one of said pair of data lines whendata is read out from the selected memory cell; and first and secondcommon potential lines for supplying each of said sense amplifiers withsaid first and second potentials for the operation thereof, said firstand second common potential lines being provided corresponding to eachof said memory arrays and connected in common to the sense amplifierscorresponding to each memory array.
 3. A semiconductor memory accordingto claim 2, wherein said first and second potentials are a supplyvoltage and a ground potential respectively.
 4. A semiconductor memoryaccording to claim 2, further comprising: shorting means for shortingsaid first and second common potential lines corresponding to each ofsaid memory arrays during the non-select period of said memory arrays,thereby forming said medium potential which is to be supplied to saidpairs of common data lines.
 5. A semiconductor memory according to claim4, wherein said voltage supply means is constituted by second switchingmeans provided between said pairs of common data lines and either saidfirst or second common potential line, said second switching means beingadapted to connect together said pairs of common data lines and eithersaid first or second common potential line when said first and secondcommon potential lines are shorted.
 6. A semiconductor memory accordingto claim 4, wherein said precharge means includes means for supplyingsaid pairs of data lines with said medium potential obtained as a resultof the shorting between said first and second common potential lines. 7.A semiconductor memory according to claim 4, wherein each of said senseamplifiers is constituted by two CMOS inverters which are cross-coupledto each other, said first and second common potential lines beingrespectively connected to the sources of P-channel MOSFETs and thesources of N-channel MOSFETs in these CMOS inverter circuits.
 8. Asemiconductor memory according to claim 4, further comprising: staticpull-up means connected to each of said pairs of common data lines.
 9. Asemiconductor memory comprising: pairs of data lines; word linesintersecting said pairs of data lines; memory cells for storing datawhich are respectively provided at the intersections between said datalines and said word lines, wherein each of said memory cells includes aMOSFET and a capacitor coupled to said MOSFET for storing said data;selecting means for selecting a predetermined one of said memory cells;sense amplifiers each respectively coupled to a corresponding pair ofdata lines, wherein each of said sense amplifiers amplifies a leveldifference between a predetermined reference potential applied to one ofsaid pair of data lines and a data potential applied to another one ofsaid pair of data lines when data is read out from a selected memorycell; a common potential line for supplying each of said senseamplifiers with a potential for the operation thereof; switching meansconnected between said pairs of data lines and said common potentialline, said switching means including means for coupling said commonpotential line to said pairs of data lines during a non-select period oftime when memory cells connected to said pairs of data lines are notselected by said selecting means to provide said pairs of data lineswith a potential level corresponding to a potential of said commonpotential line during said non-select period; and reference potentialgenerating means for providing said reference potential to said commonpotential line during said non-select period.
 10. A semiconductor memoryaccording to claim 9, wherein said common potential line is comprised offirst and second common potential lines for supplying said senseamplifier with a supply voltage and a ground potential, respectively,the potential of said common potential line during the non-select periodof said memory cells being made medium between said supply voltage andsaid ground voltage as a result of shorting between said first andsecond common potential lines.
 11. A semiconductor memory comprising: aplurality of memory arrays each of which includes a plurality of firstdata lines, a plurality of first word lines intersecting said datalines, memory cells respectively provided at the intersections betweensaid first data lines and said word lines, a plurality of second datalines, a plurality of second word lines intersecting said second datalines and memory cells respectively provided at the intersectionsbetween said second data lines and said second word lines, wherein eachof said memory cells includes a MOSFET and a capacitor coupled to saidMOSFET for storing data; precharge means coupled to said first andsecond data lines and for precharging said first and second data linesto a reference potential whose level is a predetermined intermediatepotential level between first and second potentials; first common datalines provided respectively corresponding to said memory arrays; secondcommon data lines provided respectively corresponding to said memoryarrays; a plurality of word selecting means provided respectivelycorresponding to said memory arrays, wherein each of said word selectingmeans selects a word line from said first word lines and said secondword lines; column selecting means provided in common with respect tosaid memory arrays, said column selecting means including means forgenerating a common column selecting signal for designating a first dataline and a second data line from said first data lines and said seconddata lines in each of said memory arrays; a plurality of columnswitching means provided respectively corresponding to said memoryarrays, each of said column switching means being responsive to saidcommon column selecting signal and including means for electricallycoupling the first and second data lines designated in the correspondingmemory array to the corresponding first and second common data lines,respectively; memory array selecting means for selecting one of saidmemory arrays so that a memory cell is selected by the respectiveoperation of said column selecting means, said plurality of wordselecting means, and said memory array selecting means; a plurality ofsense amplifiers each of which is coupled to one of said first datalines and to one of said second data lines, wherein each of said senseamplifiers amplifies a level difference between said reference potentialon one data line of the first and second data lines and an informationpotential on the other data line of said first and second data lines,wherein said information potential occurs on said other data line by theselection of the memory cell coupled to said other data line; andvoltage supply means for supplying a potential having a substantiallyidentical potential to said reference potential to first and secondcommon data lines corresponding to a memory array which is not selectedby said memory array selecting means when said memory array selectingmeans selects one of said memory arrays.
 12. A semiconductor memoryaccording to claim 11, wherein the level difference between said firstand second potentials corresponds to the level difference obtained bythe operation of the sense amplifier on the first and send data lines.13. A semiconductor memory according to claim 12, wherein said voltagesupply means includes means for supplying a third potential having apredetermined level between said first potential and said referencepotential.
 14. A semiconductor memory according to claim 13, whereinsaid first and second potentials are a supply voltage and a groundpotential respectively.
 15. A semiconductor memory according to claim14, wherein each of said first data lines and each of said second datalines are a pair.
 16. A semiconductor memory according to claim 15,wherein each of said first data lines and each of said second data linesare a pair.
 17. A semiconductor memory according to claim 16, furthercomprising a first power line for receiving said power voltage and asecond power line for receiving said ground potential, wherein each ofsaid sense amplifiers includes a first CMOS inverter circuit coupledbetween said first and second power lines and a second CMOS invertercircuit coupled between said first and second power lines.
 18. Asemiconductor memory according to claim 17, further comprising: staticpull-up means connected to each of said first and second common datalines.
 19. A semiconductor memory according to claim 13, wherein saidprecharge means includes reference potential generating means forgenerating said reference potential and switching means for supplyingsaid reference potential to the first and second common data lines whichcorrespond to the non-selected memory array when said memory arrayselecting means selects one of said memory arrays.
 20. A semiconductormemory according to claim 19, wherein said reference potentialgenerating means includes a plurality of reference potential generatorsprovided respectively corresponding to said memory arrays, wherein eachof said reference potential generators generates said referencepotential when the corresponding memory array is not selected by saidmemory array selecting means.
 21. A semiconductor memory comprising: aplurality of memory arrays each including pairs of data lines, wordlines intersecting said pairs of data lines, and memory cellsrespectively provided at the intersections between said pairs of datalines and said word lines, wherein each of said memory cells includes aMOSFET and a capacitor coupled to said MOSFET for storing data;precharge means for precharging said pairs of data lines to a firstinternal potential being substantially medium between first and secondpotentials; pairs of common data lines provided respectivelycorresponding to said memory arrays; column switches which are providedbetween each of said pairs of common data lines and each of said pairsof data lines in the memory array which said column switchesrespectively corresponds to; a row address decoder which outputs a wordline select signal; a column address decoder which is provided in commonwith respect to said memory arrays, wherein said column address decoderoutputs a common column selecting signal and each of said pairs ofcommon data lines are connected respectively to one pair of data linesselected from among said pairs of data lines in each of said memoryarrays by means of said column switches on the basis of said commoncolumn selecting signal; sense amplifiers provided respectivelycorresponding to said pairs of data lines; a main amplifier connected toone of said pairs of common data lines; a pull-up circuit which suppliesone of said pairs of common data lines, corresponding to one of saidmemory arrays in which a selected word line is included, with a secondinternal potential being different from said first internal potential;and switch circuits which supply a potential having a substantiallyidentical potential to said first internal potential to a pair of commondata lines corresponding to a memory array in which a selected word lineis not included; wherein a first one of said column switches connectedto one of pairs of said common data lines, corresponding to one of saidmemory arrays in which a selected word line is included, and a secondone of column switches connected to one of pairs of said common datalines, corresponding to one of said memory arrays in which a selectedword line is not included, are switched by said common column selectingsignal, and wherein ones of said sense amplifiers, corresponding to oneof said memory arrays in which a selected word line is included, aremade operative, and others of said sense amplifiers, corresponding toone of said memory arrays in which a selected word line is not included,are made inoperative.
 22. A semiconductor memory according to claim 21,wherein, in a first period, said precharge means supplies said pairs ofdata lines with said first internal potential and said switch circuitssupplies said pairs of common data lines with a potential beingsubstantially equal to said first internal potential, and wherein, in asecond period following said first period, said pull-up circuit suppliesone of said pairs of common data lines, corresponding to one of saidmemory arrays in which a selected word line is included, with saidsecond internal potential.
 23. A semiconductor memory according to claim22, wherein, in said first period, said switch circuits are controlledby a row address strobe signal regardless of a memory array selectsignal and supplies said pairs of common data lines with said potentialbeing substantially equal to said first internal potential, wherein, insaid second period, said switch circuits are controlled by said memoryarray select signal and said row address strobe signal and supplies oneof said pairs of common data lines, corresponding to one of said memoryarrays in which a selected word line is not included, with saidpotential being substantially equal to said first internal potential,wherein, in said second period, said pull-up circuit are controlled bysaid memory array select signal and said row address strobe signal andsupplies one of said pairs of common data lines, corresponding to one ofsaid memory arrays in which a selected word line is included, with saidsecond internal potential.
 24. A semiconductor memory according to claim22, wherein, in said first period, said switch circuits supply saidpairs of common data lines with said potential being substantially equalto said first internal potential, wherein, in said second period, saidswitch circuits supply one of said pairs of common data lines,corresponding to one of said memory arrays in which a selected word lineis not included, with said potential being substantially equal to saidfirst internal potential, wherein, in said second period, said pull-upcircuit supplies one of said pairs of common data lines, correspondingto one of said memory arrays in which a selected word line is included,with said second internal potential, and wherein said first periodcorresponds to a non-selected state of said semiconductor memory andsaid second period corresponds to a selected state of said semiconductormemory.
 25. A semiconductor memory according to claim 21, wherein saidfirst one of column switches, said second one of column switches andsaid column address decoder are connected by a data line select line.26. A semiconductor memory according to claim 21, wherein said firstpotential is substantially medium between the levels obtained by theoperation of said sense amplifier on the pair of data lines, and whereinsaid second internal potential is higher than said first internalpotential.